Semiconductor memory device

ABSTRACT

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of PCT International ApplicationPCT/JP2011/005991 filed on Oct. 26, 2011, which claims priority toJapanese Patent Application No. 2010-280989 filed on Dec. 16, 2010. Thedisclosures of these applications including the specifications, thedrawings, and the claims are hereby incorporated by reference in theirentirety.

BACKGROUND

The present disclosure relates to semiconductor memory devices, and moreparticularly, to a semiconductor memory device in which the number ofcomponents is reduced while data destruction in a non-selected memorycell during data write operation is reduced.

In conventional static random access memory (SRAM) devices, the furtherminiaturization of transistors included in a memory cell would increasesignificant variations in transistor characteristics, disadvantageouslyleading to destruction of data stored by the memory cell during memoryoperation.

There is a technique of reducing or preventing data destruction duringread operation in which bit lines are provided for write operation andread operation separately.

There is also a technique of reducing or preventing data destruction ina non-selected memory cell during write operation in which data readfrom the non-selected memory cell is written back to the non-selectedmemory cell (restore or write-back technique) (see Japanese PatentPublication No. 2007-4888 and International Publication WO/2008/032549).

On the other hand, there is also a known technique of using ahierarchical bit line architecture in which a local bit line connecteddirectly to a memory cell has a short line length, and a local senseamplifier (SA) circuit is provided for each local bit line (see JapanesePatent Publication No. 2000-207886 and K. Takeda, et al., “Multi-stepWord-line Control Technology in Hierarchical Cell Architecture forScaled-down High-density SRAMs,” Technical Digest of Technical Papers,2010 Symposium on VLSI Circuits, pp. 101-102).

A local SA circuit provided in the conventional hierarchical bit linearchitecture includes 22 components for each bit line when the local SAcircuit is of single end type (see Japanese Patent Publication No.2000-207886), and eight components for each bit line when the local SAcircuit is of cross-coupled type (see K. Takeda, et al.). The areaoverhead of the SRAM device is disadvantageously large.

SUMMARY

The present disclosure describes implementations of a semiconductormemory device in which the number of components in the SA circuit whiledata destruction in the memory cell is reduced or prevented.

An example semiconductor memory device includes a first and a secondsignal line forming a pair of signal lines, a third and a fourth signalline forming another pair of signal lines, a memory cell connected tothe first and second signal lines, and an SA circuit provided betweenthe first and second signal lines and the third and fourth signal lines.The SA circuit includes six transistors, i.e., a first transistor of afirst conductivity type having a gate connected to a precharge signal, asource connected to a first power supply potential, and a drainconnected to the first signal line, a second transistor of the firstconductivity type having a gate connected to the precharge signal, asource connected to the first power supply potential, and a drainconnected to the second signal line, a third transistor of the firstconductivity type having a gate connected to the first signal line, asource connected to the first power supply potential, and a drainconnected to the third signal line, a fourth transistor of the firstconductivity type having a gate connected to the second signal line, asource connected to the first power supply potential, and a drainconnected to the fourth signal line, a fifth transistor of a secondconductivity type having a gate connected to the third signal line, asource connected to a second power supply potential, and a drainconnected to the first signal line, and a sixth transistor of the secondconductivity type having a gate connected to the fourth signal line, asource connected to the second power supply potential, and a drainconnected to the second signal line.

Another example semiconductor memory device includes memory cells, bitlines each connected to corresponding ones of the memory cells, andsense amplifier circuits each connected to corresponding ones of the bitlines. Each of the sense amplifier circuits has a single-endconfiguration and a function of writing data read from a correspondingone of the memory cells back to the corresponding bit lines, andachieves data write operation to a corresponding one of the memory cellsby the function of writing data back to the corresponding bit lines.

According to the present disclosure, the function of writing data storedby a non-selected memory cell during write operation back to the memorycell without the need of a fine timing control is provided, whereby asemiconductor memory device can be provided in which the number ofcomponents in the SA circuit is reduced while data destruction in thememory cell is reduced or prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a main configuration of asemiconductor memory device according to a first embodiment of thepresent disclosure.

FIG. 2 is a circuit diagram showing a detailed example configuration ofa memory cell of FIG. 1.

FIG. 3 is a circuit diagram showing a detailed example configuration ofa local SA circuit of FIG. 1.

FIG. 4 is a timing chart showing main operation of the semiconductormemory device of the first embodiment of the present disclosure.

FIG. 5 is a block diagram showing a main configuration of asemiconductor memory device according to a second embodiment of thepresent disclosure.

FIG. 6 is a circuit diagram showing a detailed example configuration ofa memory cell of FIG. 5.

FIG. 7 is a timing chart showing main operation of the semiconductormemory device of the second embodiment of the present disclosure.

FIG. 8 is a block diagram showing a main configuration of asemiconductor memory device according to a third embodiment of thepresent disclosure.

FIG. 9 is a circuit diagram showing a detailed example configuration ofa local SA circuit of FIG. 8.

FIG. 10 is a block diagram showing a main configuration of asemiconductor memory device according to a fourth embodiment of thepresent disclosure.

FIG. 11 is a circuit diagram showing a detailed example configuration ofa local SA circuit of FIG. 10.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detailhereinafter with reference to the accompanying drawings. Note that thesame or like parts are indicated by the same reference characters andwill not be redundantly described in the embodiments described below.

First Embodiment

FIG. 1 is a block diagram showing a main configuration of asemiconductor memory device according to a first embodiment of thepresent disclosure. The semiconductor memory device of FIG. 1 includesmemory cells (MCs) 1, memory cell arrays 3 in which the memory cells 1are arranged in a matrix, word lines WL<0>-WL<3> which are used tocontrol input and output of data in the memory cells 1, a row decoder 5which selects and activates the word lines, local SA circuits 2, localbit lines (pairs of signal lines) LBL<0>/NLBL<0>-LBL<3>/NLBL<3> whichconnect the memory cells 1 and the local SA circuits 2, local SA controlcircuits 6 which control precharge signals PC<0>-PC<1> of the local SAcircuits 2, global bit lines (pairs of signal lines) GBL<0>/NGBL<0> andGBL<1>/NGBL<1> connected to the local SA circuits 2, an interface (IF)circuit 7 which has a function of selecting one of the global bit linepairs GBL<0>/NGBL<0> and GBL<1>/NGBL<1>, and a clock signal CLK, a datainput signal DI, and a data output signal DO which are connected to theIF circuit 7. Although FIG. 1 shows only eight memory cells 1 for thesake of simplicity, any number of memory cells 1 may be provided. Also,any numbers of word lines, local bit lines, and global bit lines may beprovided.

In particular, FIG. 1 shows the semiconductor memory device having ahierarchical bit line architecture which includes the local bit linesLBL<0>/NLBL<0>-LBL<3>/NLBL<3> which are connected directly to the memorycells 1 arranged in specific groups and and have a short line length,and the global bit lines GBL<0>/NGBL<0> and GBL<1>/NGBL<1> which areprovided on the memory cell arrays 3 and connected to all the local bitlines via the local SA circuits 2 and have a long line length.

FIG. 2 is a circuit diagram showing a detailed example configuration ofthe memory cell 1 of FIG. 1. As shown in FIG. 2, the memory cell 1includes a first cell transistor 21 a, a second cell transistor 21 b, athird cell transistor 22 a, a fourth cell transistor 22 b, a fifth celltransistor 23 a, and a sixth cell transistor 23 b. The first celltransistor 21 a is a P-channel transistor having a source connected to aVDD potential, a drain connected to a first memory node, and a gateconnected to a second memory node. The second cell transistor 21 b is aP-channel transistor having a source connected to the VDD potential, adrain connected to the second memory node, and a gate connected to thefirst memory node. The third cell transistor 22 a is an N-channeltransistor having a source connected to a VSS potential, a drainconnected to the first memory node, and a gate connected to the secondmemory node. The fourth cell transistor 22 b is an N-channel transistorhaving a source connected to the VSS potential, a drain connected to thesecond memory node, and a gate connected to the first memory node. Thefifth cell transistor 23 a is an N-channel transistor having a sourceconnected to the first memory node, a drain connected to the local bitline LBL, and a gate connected to the word line WL. The sixth celltransistor 23 b is an N-channel transistor having a source connected tothe second memory node, a drain connected to the local bit line NLBL,and a gate connected to the word line WL.

FIG. 3 is a circuit diagram showing a detailed example configuration ofthe local SA circuit 2 of FIG. 1. As shown in FIG. 3, the local SAcircuit 2 includes a first transistor 10 a, a second transistor 10 b, athird transistor 8 a, a fourth transistor 8 b, a fifth transistor 9 a,and a sixth transistor 9 b. The first transistor 10 a is a P-channeltransistor having a gate connected to the precharge signal PC, a sourceconnected to the VDD potential, and a drain connected to the local bitline LBL. The second transistor 10 b is a P-channel transistor having agate connected to the precharge signal PC, a source connected to the VDDpotential, and a drain connected to the local bit line NLBL. The thirdtransistor 8 a is a P-channel transistor having a gate connected to thelocal bit line LBL, a source connected to the VDD potential, and a drainconnected to the global bit line GBL. The fourth transistor 8 b is aP-channel transistor having a gate connected to the local bit line NLBL,a source connected to the VDD potential, and a drain connected to theglobal bit line NGBL. The fifth transistor 9 a is an N-channeltransistor having a gate connected to the global bit line GBL, a sourceconnected to the VSS potential, and a drain connected to the local bitline LBL. The sixth transistor 9 b is an N-channel transistor having agate connected to the global bit line NGBL, a source connected to theVSS potential, and a drain connected to the local bit line NLBL.

As described above, the local SA circuit 2 of FIG. 3 is controlled basedon the precharge signal PC, and includes the P-channel transistors 10 aand 10 b for precharging the local bit lines LBL and NLBL to a highlevel (a power supply potential or the VDD potential), the P-channeltransistors 8 a and 8 b for transferring to the global bit lines GBL andNGBL data driven depending on the potential levels of the local bitlines LBL and NLBL, respectively, and the N-channel transistors 9 a and9 b for transferring to the local bit lines LBL and NLBL data drivendepending on the potential levels of the global bit lines GBL and NGBL,respectively. Each of the pair of the P-channel transistor 8 a and theN-channel transistor 9 a and the pair of the P-channel transistor 8 band the N-channel transistor 9 b has a feedback structure in which datais fed back, depending on the potential level.

FIG. 4 is a timing chart showing main operation of the semiconductormemory device of the first embodiment of the present disclosure. Writeoperation and read operation of the semiconductor memory device havingthe above configuration will be described with reference to the timingchart of FIG. 4.

Initially, when a write command is externally input at time A, writeoperation is performed. When data DI0 is input from the data inputsignal DI, the data DI0 is transferred to the global bit lines GBL<1>and NGBL<1> selected by the IF circuit 7. Next, when the prechargesignal PC<0> goes high, precharge operation to the local bit lines ofthe local SA circuit 2 connected to the precharge signal PC<0>becomesinactive. Next, when the word line WL<0> is activated to a high signal,the memory cells 1 connected to the word line WL<0> are connected to therespective corresponding local bit line pairs LBL<0>/NLBL<0> andLBL<2>/NLBL<2>. At this time, when the voltage of the global bit lineGBL<1> which is a signal of a selected column exceeds the thresholdvoltage of the N-channel transistor so that the logical value of theglobal bit line GBL<1> goes high, only the N-channel transistor 9 a inthe local SA circuit 2 is activated, and only the local bit line LBL<2>is pulled down to a ground potential (the VSS potential), i.e., low datais written. At this time, when the low level of the local bit lineLBL<2> becomes higher than or equal to the threshold voltage of theP-channel transistor, the P-channel transistor 8 a writes high data tothe global bit line GBL<0> (i.e., a so-called feedback function),thereby assisting in increasing the transfer rate of data to the localSA circuit 2 in addition to the normal operation. Because the global bitline NGBL<1> is low, the N-channel transistor 9 b in the local SAcircuit 2 is not activated.

On the other hand, the global bit lines GBL<0> and NGBL<O> connected tothe non-selected column are in a state (Hi-Z state) released from theprecharged state and are on standby. In other words, although writeoperation is not performed on the memory cells 1 connected to the localbit lines LBL<0> and NLBL<0>, the memory cell 1 and the local bit linesLBL<0> and NLBL<0> are connected together by the word line WL<0>, whichstate is a so-called half-selected state during write operation.Initially, data stored by the memory cell 1 connected to the word lineWL<0> is read out to the local bit lines LBL<0> and NLBL<0>. At thistime, when the voltage of the local bit line LBL<0> exceeds thethreshold voltage of the P-channel transistor to go low, the P-channeltransistor 8 a of the local SA circuit 2 is activated to cause theglobal bit line GBL<0> to go high. As a result, when the global bit lineGBL<0> exceeds the threshold voltage of the N-channel transistor, theN-channel transistor 9 a is activated to perform feedback operation tocause the local bit line LBL<0> to go low. Because the local bit lineNLBL<0> is high, the P-channel transistor 8 b of the local SA circuit 2is not activated, and therefore, the global bit line NGBL<0> is alsomaintained low, and the P-channel transistor 9 b is not activated, sothat the local bit line NLBL<0> is maintained high.

Next, when a read command is externally input at time B, read operationis performed. When the precharge signal PC<0>goes high, prechargeoperation to the local bit lines of the local SA circuit 2 connectedthereto is inactivated. Next, when the word line WL<0>is activated to ahigh signal, the memory cells 1 connected thereto are connected to therespective corresponding local bit line pairs LBL<0>/NLBL<0> andLBL<2>/NLBL<2>. Operation of transferring data to the global bit linesGBL<0> and NGBL<0> using the local SA circuit 2 is exactly the same asoperation of transferring data to the global bit lines GBL<1> andNGBL<1>, and therefore, only the global bit lines GBL<0> and NGBL<0>will be described. In this case, when data stored by the memory cell 1causes the voltage of the local bit line LBL<0> to exceed the thresholdvoltage of the P-channel transistor, i.e., the local bit line LBL<0>goes low, the P-channel transistor 8 a of the local SA circuit 2 isactivated, so that high data is transferred to the global bit lineGBL<0>. At the same time, when the voltage of the global bit line GBL<0>exceeds the threshold voltage of the N-channel transistor, i.e., theglobal bit line GBL<0> goes high, the N-channel transistor 9 a isactivated, so that by feedback operation, the local bit line LBL<0> ispulled down to go low. On the other hand, data stored by the memory cell1 causes the local bit line NLBL<0> to be maintained high, andtherefore, the P-channel transistor 8 b of the local SA circuit 2 is notactivated, and therefore, the global bit line NGBL<0> is also maintainedlow. At the same time, the N-channel transistor 9 b is not activated. Bythe above operation, data read from the memory cell 1 is transferred tothe global bit lines GBL<0> and NGBL<0>, and similarly, data istransferred to the global bit lines GBL<1> and NGBL<1>. One of the twopieces of data is selected by the IF circuit 7 and is output as theoutput data DO0 from the data output signal DO to circuitry external tothe memory device (time C).

As described above, in the non-selected memory cell 1 during writeoperation, only low data read from the memory cell 1 is automaticallyrestored by the feedback function which is performed by the P-channeltransistor 8 a and the N-channel transistor 9 a, or the P-channeltransistor 8 b and the N-channel transistor 9 b, in the local SA circuit2. Therefore, the static noise margin (SNM) of the non-selected memorycell 1 is significantly improved.

The N-channel transistors 9 a and 9 b in the local SA circuit 2 functionas a write buffer circuit during write operation. However, theinterconnect load of the local bit line is considerably small, and onlyone stage of N-channel transistor is provided. Therefore, a sufficientlevel of write performance can be achieved, and a large driver size isnot required, whereby the area can be effectively reduced.

The signal transferred to the global bit line selected during writeoperation may be a control signal for the N-channel transistors 9 a and9 b for writing data to the memory cell 1 via the local bit line, andtherefore, a high level of drive performance is not required. This meansthat it is not necessary to increase a driver circuit which drives acontrol signal included in the IF circuit 7 for the global bit linewhose interconnect load is relatively large because the global bit lineis provided on the memory cell array 3, and therefore, the memory areaand the instantaneously consumed current can be effectively reduced. Asthe control signal transferred to the global bit line, low (groundpotential or VSS) precharge is used on the global bit line, andtherefore, high data only needs to be driven. Therefore, the performanceof the N-channel transistor included in the driver circuit can befurther reduced, and therefore, it is expected that the area can beadvantageously reduced. By the feedback function in the local SA circuit2 (i.e., the local bit line is pulled down by the transfer of high dataon the global bit line, so that the global bit line is pulled up to gohigh), the driver circuit can assist the global bit line in going high,whereby the speed of transmission of the control signal can beincreased, and the area of the driver circuit can be reduced. Inparticular, write operation of the SRAM memory cell typically tends tobe most difficult under processing conditions that the threshold voltageof the P-channel transistor is low and the threshold voltage of theN-channel transistor is high. Under the processing conditions, in thissemiconductor memory device in which the global bit line having a largeload is driven to the high level, i.e., the P-channel transistor isactivated, the speed can be advantageously increased compared to whenthe bit line having a large load is driven by the N-channel transistor.Moreover, in this semiconductor memory device in which the N-channeltransistor only drives the local bit lines having a low load, the writeperformance can be improved compared to the conventional art.

Next, during read operation, low data read to the local bit line can betransferred to the global bit line by the P-channel transistor withoutan unnecessary timing control. Therefore, in particular, this isconsiderably effective compared to the difficulty in the control ofactivation timing of a conventional cross-coupled SA circuit duringhigh-speed operation, and high-speed operation can be achieved while thenumber of components can be reduced, and therefore, the area can beeffectively reduced. When high data is read to the global bit lines, thelocal bit lines are pulled down by the feedback function of theN-channel transistors 9 a and 9 b, resulting in higher-speed readoperation which may assist in read operation of low data to the localbit lines.

For the non-selected memory cell during read operation, the SNM can besignificantly improved by the restore function which can be achieved bythe local SA circuit 2 in the non-selected memory cell.

Compared to the conventional cross-coupled SA circuit, the local SAcircuit 2 of FIG. 3 can be implemented by a small number of components,and operation can be achieved without complicated activation timing(timing-free operation), whereby a reduction in area and an increase inspeed can be simultaneously achieved. In particular, in the hierarchicalbit line architecture of FIG. 1 in which the interconnect load of thelocal bit line is reduced so that, during read operation, the potentiallevels of the local bit lines quickly exceed the threshold voltages ofthe P-channel transistors 8 a and 8 b, the speed of the memory devicecan be effectively increased.

Note that even if the local SA circuit 2 of FIG. 3 is used in a bit lineconfiguration which is not of hierarchical type on the memory cell array3, the area can be effectively reduced and the control timing can beeffectively facilitated. The local SA circuit 2 may be provided betweenthe separated memory cell arrays 3. Moreover, by arranging the two localSA circuits 2 to be adjacent to each other, the number of layoutseparation regions between the local SA circuit 2 and the memory cellarray 3 can be halved, whereby the area can be effectively reduced.

Although only the precharge signal PC<0> is high in this embodiment, allof the precharge signals PC<0>-PC<1> may be simultaneously high in orderto reduce or avoid an increase in a through current during writeoperation.

Although the SRAM memory cell is illustrated in this embodiment, thepresent disclosure is, of course, applicable to any memory devices thatrequire similar memory operation.

Second Embodiment

FIG. 5 is a block diagram showing a main configuration of asemiconductor memory device according to a second embodiment of thepresent disclosure. FIG. 6 is a circuit diagram showing a detailedexample configuration of a memory cell 11 of FIG. 5. The secondembodiment is clearly different from the first embodiment in that thememory cell 11 of the second embodiment includes word lines WLA and WLBshown in FIG. 6.

As shown in FIG. 6, the memory cell 11 includes a first cell transistor21 a, a second cell transistor 21 b, a third cell transistor 22 a, afourth cell transistor 22 b, a fifth cell transistor 23 a, and a sixthcell transistor 23 b. The first cell transistor 21 a is a P-channeltransistor having a source connected to the VDD potential, a drainconnected to the first memory node, and a gate connected to the secondmemory node. The second cell transistor 21 b is a P-channel transistorhaving a source connected to the VDD potential, a drain connected to thesecond memory node, and a gate connected to the first memory node. Thethird cell transistor 22 a is an N-channel transistor having a sourceconnected to the VSS potential, a drain connected to the first memorynode, and a gate connected to the second memory node. The fourth celltransistor 22 b is an N-channel transistor having a source connected tothe VSS potential, a drain connected to the second memory node, and agate connected to the first memory node. The fifth cell transistor 23 ais an N-channel transistor having a source connected to the first memorynode, a drain connected to the local bit line LBL, and a gate connectedto the first word line WLA. The sixth cell transistor 23 b is anN-channel transistor having a source connected to the second memorynode, a drain connected to the local bit line NLBL, and a gate connectedto the second word line WLB different from the first word line WLA.

FIG. 7 is a timing chart showing main operation of the semiconductormemory device of the second embodiment of the present disclosure. Readoperation of the semiconductor memory device having the aboveconfiguration will be described with reference to the timing chart ofFIG. 7.

Initially, when a read command is externally input at time A, readoperation is performed. When the precharge signal PC<0> goes high,precharge operation to the local bit lines of the local SA circuit 2connected thereto becomes inactive. Next, the word lines WLA<1> andWLB<0> are activated to the high signal, the memory cells 11 connectedthereto are connected to the respective corresponding local bit linepairs LBL<0>/NLBL<0> and LBL<2>/NLBL<2>. The operation of transferringdata to the global bit lines GBL<0> and NGBL<0> and the global bit linesGBL<1>and NGBL<1> using the local SA circuits 2 is the same as that ofthe first embodiment and will not be described. At this time, data onthe local bit line NLBL<0> read from the memory cell 11 connected to theword line WLB<0>, and data on the local bit line LBL<2>read from thememory cell 11 connected to the word line WLA<1>, are transferred to theglobal bit lines NGBL<0> and GBL<1> because the memory cells are in thenon-selected state, and are not output as output data by the IF circuit7 performing the non-selection control. In other words, only data on thelocal bit lines LBL<0> and NLBL<2> are output, i.e., data can besimultaneously read from different memory cells 11 (multiport memoryfunction).

Next, the same operation is preformed from time B to time C, except thatthe word lines WLA<0> and WLB<1> are activated.

As described above, data can be simultaneously read to data outputsignals DOA and DOB from two different memory cells during readoperation, i.e., a multiport memory device can be easily obtained. Inparticular, a multiport memory device can be implemented using thememory cell 11 of FIG. 6 including six transistors. Therefore, the areacan be significantly reduced compared to a conventional multiport memorydevice including eight transistors.

Third Embodiment

FIG. 8 is a block diagram showing a main configuration of asemiconductor memory device according to a third embodiment of thepresent disclosure. FIG. 9 is a circuit diagram showing a detailedexample configuration of a local SA circuit 13A of FIG. 8. In FIG. 8,the local SA circuit 13A of FIG. 9 and a local SA control circuit 12 areblocks clearly different from those of the first embodiment of FIG. 1.The local SA circuit 13A of FIG. 9 is the above local SA circuit 2 inwhich an additional N-channel transistor 14 is provided at the sourcesof the N-channel transistors 9 a and 9 b, and is controlled based on acontrol signal NSE generated by the local SA control circuit 12.

Write operation and read operation of the semiconductor memory devicethus configured can be represented by the timing chart of FIG. 4 towhich only the control signal NSE<0> is added. The control signal NSE<0>is a column selection signal, and may have the same logical value asthat of the precharge signal PC<0>, and may go high at the same timingas or slightly later than the precharge signal PC<0>, and go low at thesame timing as that of the precharge signal PC<0>. The other controlsignal NSE<1> is maintained low.

According to this embodiment, in addition to the advantages of the firstembodiment, the control signal NSE<1> other than the control signalNSE<0> connected to the local SA circuit 13A connected to the selectedmemory cell 1 is maintained low. As a result, it is possible to preventoperation of writing data on the global bit lines GBL<0> and NGBL<0> andthe global bit lines GBL<1> and NGBL<1> to the local bit lines LBL<1>and NLBL<1> and the local bit lines LBL<3> and NLBL<3> connected to thenon-selected memory cells 1 via the global bit lines GBL<0> and NGBL<0>and the global bit lines GBL<1> and NGBL<1> and the local SA circuits13A. In other words, it is possible to reduce consumption of uselessprecharge power of the local bit line which is caused by one of thelocal bit line LBL<1> or NLBL<1> and the local bit line LBL<3> orNLBL<3> being pulled down by the N-channel transistor 9 a or 9 b of thelocal SA circuit 13A.

Although only the precharge signal PC<0> is high in this embodiment, allof the precharge signals PC<0>-PC<1> may be simultaneously high in orderto reduce or avoid an increase in a through current during writeoperation. The control signal NSE may, of course, be generated by thelogical product of the column selection signal and the timing controlsignal required for memory operation.

Fourth Embodiment

FIG. 10 is a block diagram showing a main configuration of asemiconductor memory device according to a fourth embodiment of thepresent disclosure. FIG. 11 is a circuit diagram showing a detailedexample configuration of a local SA circuit 13B of FIG. 10. In FIG. 10,the local SA circuit 13B of FIG. 11 and a local SA control circuit 12are blocks clearly different from those of the first embodiment ofFIG. 1. The local SA circuit 13B of FIG. 11 is the above local SAcircuit 2 in which a control signal NSE is connected to the sources ofthe N-channel transistors 9 a and 9 b.

Write operation and read operation of the semiconductor memory devicethus configured can be represented by the timing chart of FIG. 4 towhich only the control signal NSE<0> is added. The control signal NSE<0>is, for example, a logical signal derived from a column selectionsignal, and may have a logical value opposite to that of the prechargesignal PC<0>, and may go low at the same timing as or slightly laterthan the precharge signal PC<0>, and go high at the same timing as thatof the precharge signal PC<0>. The other control signal NSE<1> ismaintained high.

According to this embodiment, in addition to the advantages of the firstembodiment, the control signal NSE<1> other than the control signalNSE<0> connected to the local SA circuit 13B connected to the selectedmemory cell 1 is maintained high. As a result, it is possible to preventoperation of writing data on the global bit lines GBL<0> and NGBL<0> andthe global bit lines GBL<1> and NGBL<1> to the local bit lines LBL<1>and NLBL<1> and the local bit lines LBL<3> and NLBL<3> connected to thenon-selected memory cells 1 via the global bit lines GBL<0> and NGBL<0>and the global bit lines GBL<1> and NGBL<1> and the local SA circuits13B. In other words, it is possible to reduce consumption of uselessprecharge power of the local bit line which is caused by one of thelocal bit line LBL<1> or NLBL<1> and the local bit line LBL<3> orNLBL<3> being pulled down by the N-channel transistor 9 a or 9 b of thelocal SA circuit 13B. In addition, the N-channel transistor 14 of thelocal SA circuit 13A of the third embodiment can be removed, whereby thearea reduction effect of the first embodiment and the low powerconsumption effect of the third embodiment can be simultaneouslyachieved. Although only the precharge signal PC<0> is high in thisembodiment, all of the precharge signals PC<0>-PC<1> may besimultaneously high in order to reduce or avoid an increase in a throughcurrent during write operation.

The first-fourth embodiments have been described. The first-fourthembodiments may be implemented in combination in any manner. Theconfiguration of FIG. 3, 9, or 11 may be used in the global SA circuit.

As described above, the semiconductor memory device of the presentdisclosure has the advantage that the number of components in the SAcircuit can be reduced while data destruction of the memory cell isreduced or prevented, and is useful, for example, for a system LSIcircuit including a large number of various memory devices.

1. A semiconductor memory device comprising: a first and a second signalline forming a pair of signal lines; a third and a fourth signal lineforming another pair of signal lines; a memory cell connected to thefirst and second signal lines; and a sense amplifier circuit providedbetween the first and second signal lines and the third and fourthsignal lines, wherein the sense amplifier circuit includes a firsttransistor of a first conductivity type having a gate connected to aprecharge signal, a source connected to a first power supply potential,and a drain connected to the first signal line, a second transistor ofthe first conductivity type having a gate connected to the prechargesignal, a source connected to the first power supply potential, and adrain connected to the second signal line, a third transistor of thefirst conductivity type having a gate connected to the first signalline, a source connected to the first power supply potential, and adrain connected to the third signal line, a fourth transistor of thefirst conductivity type having a gate connected to the second signalline, a source connected to the first power supply potential, and adrain connected to the fourth signal line, a fifth transistor of asecond conductivity type having a gate connected to the third signalline, a source connected to a second power supply potential, and a drainconnected to the first signal line, and a sixth transistor of the secondconductivity type having a gate connected to the fourth signal line, asource connected to the second power supply potential, and a drainconnected to the second signal line.
 2. The semiconductor memory deviceof claim 1, wherein the first and second signal lines are local bitlines, the third and fourth signal lines are global bit lines, the localand global bit lines form a hierarchical bit line architecture.
 3. Thesemiconductor memory device of claim 1, wherein the memory cell includesa first cell transistor of the first conductivity type having a sourceconnected to the first power supply potential, a drain connected to afirst memory node, and a gate connected to a second memory node, asecond cell transistor of the first conductivity type having a sourceconnected to the first power supply potential, a drain connected to thesecond memory node, and a gate connected to the first memory node, athird cell transistor of the second conductivity type having a sourceconnected to the second power supply potential, a drain connected to thefirst memory node, and a gate connected to the second memory node, afourth cell transistor of the second conductivity type having a sourceconnected to the second power supply potential, a drain connected to thesecond memory node, and a gate connected to the first memory node, afifth cell transistor of the second conductivity type having a sourceconnected to the first memory node, a drain connected to the firstsignal line, and a gate connected to a word line, and a sixth celltransistor of the second conductivity type having a source connected tothe second memory node, a drain connected to the second signal line, anda gate connected to the word line.
 4. The semiconductor memory device ofclaim 1, wherein the memory cell includes a first cell transistor of thefirst conductivity type having a source connected to the first powersupply potential, a drain connected to a first memory node, and a gateconnected to a second memory node, a second cell transistor of the firstconductivity type having a source connected to the first power supplypotential, a drain connected to the second memory node, and a gateconnected to the first memory node, a third cell transistor of thesecond conductivity type having a source connected to the second powersupply potential, a drain connected to the first memory node, and a gateconnected to the second memory node, a fourth cell transistor of thesecond conductivity type having a source connected to the second powersupply potential, a drain connected to the second memory node, and agate connected to the first memory node, a fifth cell transistor of thesecond conductivity type having a source connected to the first memorynode, a drain connected to the first signal line, and a gate connectedto a first word line, and a sixth cell transistor of the secondconductivity type having a source connected to the second memory node, adrain connected to the second signal line, and a gate connected to asecond word line different from the first word line.
 5. Thesemiconductor memory device of claim 1, wherein the sense amplifiercircuit further includes a seventh transistor of the second conductivitytype having a drain connected to the sources of the fifth and sixthtransistors, a source connected to the second power supply potential,and a gate connected to a control signal derived from a column selectionsignal.
 6. The semiconductor memory device of claim 1, wherein thepotential value of the second power supply potential connected to thesources of the fifth and sixth transistors is controlled based on acontrol signal derived from a column selection signal.
 7. Asemiconductor memory device comprising: memory cells; bit lines eachconnected to corresponding ones of the memory cells; and sense amplifiercircuits each connected to corresponding ones of the bit lines, whereineach of the sense amplifier circuits has a single-end configuration anda function of writing data read from a corresponding one of the memorycells back to the corresponding bit lines, and achieves data writeoperation to a corresponding one of the memory cells by the function ofwriting data back to the corresponding bit lines.
 8. The semiconductormemory device of claim 7, wherein the bit lines have a hierarchicalarchitecture divided in memory cell arrays.
 9. The semiconductor memorydevice of claim 7, wherein the function of writing data back to the bitline is a function of writing back one of high data and low data. 10.The semiconductor memory device of claim 7, wherein each of the senseamplifier circuits is provided between separated memory cell arrays. 11.The semiconductor memory device of claim 10, wherein two of the senseamplifier circuits connected to two separated ones of the bit lines arearranged adjacent to each other.